There has been known a technique (chip on glass (COG)) of mounting a semiconductor chip having a lower surface provided with a plurality of bumps, on a substrate with an anisotropic conductive film interposed therebetween.
Patent Literature 1 discloses a configuration in which a plurality of bumps provided on a semiconductor chip includes first bumps arrayed close to a chip end surface and connected to first terminals provided on a substrate, and second bumps arrayed far from the chip end surface (closer to the innermost portion of the chip) and connected to second terminals provided on the substrate. In the configuration disclosed in Patent Literature 1, the second bumps are larger in area than the first bumps and the second terminals are larger in area than the first terminals. This configuration allows, upon mounting in accordance with the COG technique, conductive particles captured by the first bumps arrayed close to the chip end surface and the first terminals to be substantially equal in number to conductive particles captured by the second bumps arrayed far from the chip end surface and the second terminals, to inhibit defective connection between the second bumps and terminal areas connected thereto.